1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a front-end portion having an interface function and a back-end portion including a memory core are integrated on an individual semiconductor chip.
2. Description of Related Art
In some semiconductor devices such as a DRAM (Dynamic Random Access Memory), a memory cell array is divided into a plurality of banks (see Japanese Patent Application Laid-open No. H11-203876). A bank is a unit capable of individually receiving commands, and each bank can operate independently of each other on a non-exclusive basis. The semiconductor device described in Japanese Patent Application Laid-open No. H11-203876 uses a memory array bank enable signal as a signal for bringing each bank to an active state, and activates an active array-voltage generator in response to the memory array bank enable signal. Thus, the signal indicating whether each bank is in the active state is used as a control signal for various circuit blocks included in the semiconductor device.
The active information of banks is also used to prevent reception of commands that cannot be executed in the active state. For example, a refresh command and the like are not to be executed unless all the banks are in inactive states. Accordingly, even if a refresh command is issued when at least one of the banks is in the active state, it is necessary to guard against the refresh command, and the active information is used also for this purpose.
On the other hand, there has recently been proposed a technique in which a so-called front-end portion performing an interface with a memory controller and a back-end portion including a memory core are integrated on an individual chip, and these chips are stacked to form a single semiconductor memory device (see Japanese Patent Application Laid-Open No. 2007-158237). According to this technique, in a core chip on which the back-end portion is integrated, a space that can be allocated to the memory core increases, whereby a storage capacity per 1 chip (per 1 core chip) can be increased. On the other hand, the interface chip on which the front-end portion is integrated can be manufactured by a process different from the process for the memory core, whereby a circuit can be formed with a high-speed transistor. Furthermore, plural core chips can be allocated to one interface chip, resulting in that a high-speed semiconductor memory device having extremely large capacity as a whole can be provided.
In the stacked semiconductor device, banks are distributed over a plurality of chips unlike in the normal semiconductor device with a one-chip configuration. Accordingly, if active information of all the banks is held on the interface chip side, it is possible to guard against the commands such as the refresh command that are not to be executed unless all the banks are in the inactive states.
However, because the stacked semiconductor device has much more banks than the normal semiconductor device with a one-chip configuration, the circuit scale of the interface chip is adversely increased if the active information of all the banks is held on the interface chip side.